/*
 * Copyright (c) 2020 - , 
 *
 * SPDX-License-Identifier: 
 *
 * Change Logs:
 * Date           Author       Notes
 * 2020-08-12     chao         first version
 */

#include <board.h>

#ifdef BSP_USING_SRAM

#define DRV_DEBUG
#define LOG_TAG             "drv.sram"
#include <drv_log.h>

#define SRAM_SIZE           ((uint32_t)0x100000)/* 1MB */
#define SRAM_BANK_ADDR      ((uint32_t)0x68000000)     
#define SRAM_DATA_WIDTH     16

#ifdef RT_USING_MEMHEAP_AS_HEAP
static struct rt_memheap system_heap;
#endif

static int SRAM_Init(void)
{
    SRAM_HandleTypeDef hsram1;
    FSMC_NORSRAM_TimingTypeDef Timing = {0};

    /** Perform the SRAM1 memory initialization sequence
    */
    hsram1.Instance = FSMC_NORSRAM_DEVICE;
    hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
    hsram1.State    = HAL_SRAM_STATE_RESET;
    /* hsram1.Init */
    hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
    hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
    hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
    hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
    hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
    hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
    hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
    hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
    hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
    hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
    hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
    hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
    hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
    /* Timing */
    Timing.AddressSetupTime = 0;
    Timing.AddressHoldTime = 0;
    Timing.DataSetupTime = 3;
    Timing.BusTurnAroundDuration = 0;
    Timing.CLKDivision = 0;
    Timing.DataLatency = 0;
    Timing.AccessMode = FSMC_ACCESS_MODE_A;
    /* ExtTiming */

    if (HAL_SRAM_Init(&hsram1, &Timing, &Timing) != HAL_OK)
    {
        LOG_E("SRAM init failed!");
        return -RT_ERROR;
    }
    else
    {
        LOG_D("sram init success, mapped at 0x%X, size is %d bytes, data width is %d", SRAM_BANK_ADDR, SRAM_SIZE, SRAM_DATA_WIDTH);
#ifdef RT_USING_MEMHEAP_AS_HEAP
        /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
        rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
#endif
    }

    /** Disconnect NADV
    */

    __HAL_AFIO_FSMCNADV_DISCONNECTED();

    return RT_EOK;
}
INIT_BOARD_EXPORT(SRAM_Init);

#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
int sram_test(void)
{
#if 1
    int i = 0;
    uint32_t start_time = 0, time_cast = 0;
#if SRAM_DATA_WIDTH == 8
    char data_width = 1;
    uint8_t data = 0;
#elif SRAM_DATA_WIDTH == 16
    char data_width = 2;
    uint16_t data = 0;
#else
    char data_width = 4;
    uint32_t data = 0;
#endif

    /* write data */
    LOG_D("Writing the %ld bytes data, waiting....", SRAM_SIZE);
    start_time = rt_tick_get();
    for (i = 0; i < SRAM_SIZE / data_width; i++)
    {
#if SRAM_DATA_WIDTH == 8
        *(__IO uint8_t *)(SRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
#elif SRAM_DATA_WIDTH == 16
        *(__IO uint16_t *)(SRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
#else
        *(__IO uint32_t *)(SRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
#endif
    }
    time_cast = rt_tick_get() - start_time;
    LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
          time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));

    /* read data */
    LOG_D("start Reading and verifying data, waiting....");
    for (i = 0; i < SRAM_SIZE / data_width; i++)
    {
#if SRAM_DATA_WIDTH == 8
        data = *(__IO uint8_t *)(SRAM_BANK_ADDR + i * data_width);
        if (data != 0x55)
        {
            LOG_E("SRAM test failed!");
            break;
        }
#elif SRAM_DATA_WIDTH == 16
        data = *(__IO uint16_t *)(SRAM_BANK_ADDR + i * data_width);
        if (data != 0x5555)
        {
            LOG_E("SRAM test failed!");
            break;
        }
#else
        data = *(__IO uint32_t *)(SRAM_BANK_ADDR + i * data_width);
        if (data != 0x55555555)
        {
            LOG_E("SRAM test failed!");
            break;
        }
#endif
    }

    if (i >= SRAM_SIZE / data_width)
    {
        LOG_D("SRAM test success!");
    }

#else

    /*写入数据计数器*/
    uint32_t counter=0;  
    /* 8位的数据 */
    uint8_t ubWritedata_8b = 0, ubReaddata_8b = 0;    
    /* 16位的数据 */
    uint16_t uhWritedata_16b = 0, uhReaddata_16b = 0; 
    /* 32位的数据 */
    uint32_t uwWritedata_32b = 0, uwReaddata_32b = 0; 

    LOG_D("Checking SRAM, 8bit/16bit/32bit...");

    /*按8位格式读写数据，并校验*/

    /* 把SDRAM数据全部重置为0 ，SRAM_SIZE是以8位为单位的 */
    for (counter = 0x00; counter < SRAM_SIZE; counter++)
    {
        *(__IO uint8_t*) (SRAM_BANK_ADDR + counter) = (uint8_t)0x0;
    }

    /* 向整个SDRAM写入数据  8位 */
    for (counter = 0; counter < SRAM_SIZE; counter++)
    {
        *(__IO uint8_t*) (SRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
    }

    /* 读取 SDRAM 数据并检测*/
    for(counter = 0; counter<SRAM_SIZE;counter++ )
    {
        ubReaddata_8b = *(__IO uint8_t*)(SRAM_BANK_ADDR + counter);

        if(ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
        {
            LOG_E("0x%02x != 0x%02x", ubReaddata_8b, (uint8_t)(ubWritedata_8b + counter));
            LOG_E("8bit data read/write error!");
            return -RT_ERROR;
        }
    }


    /*按16位格式读写数据，并检测*/

    /* 把SDRAM数据全部重置为0 */
    for (counter = 0x00; counter < SRAM_SIZE/2; counter++)
    {
        *(__IO uint16_t*) (SRAM_BANK_ADDR + 2*counter) = (uint16_t)0x00;
    }

    /* 向整个SDRAM写入数据  16位 */
    for (counter = 0; counter < SRAM_SIZE/2; counter++)
    {
        *(__IO uint16_t*) (SRAM_BANK_ADDR + 2*counter) = (uint16_t)(uhWritedata_16b + counter);
    }

    /* 读取 SDRAM 数据并检测*/
    for(counter = 0; counter<SRAM_SIZE/2;counter++ )
    {
        uhReaddata_16b = *(__IO uint16_t*)(SRAM_BANK_ADDR + 2*counter);

        if(uhReaddata_16b != (uint16_t)(uhWritedata_16b + counter))
        {
            LOG_E("16bit data read/write error!");
            return -RT_ERROR;
        }
    }


    /*按32位格式读写数据，并检测*/

    /* 把SDRAM数据全部重置为0 */
    for (counter = 0x00; counter < SRAM_SIZE/4; counter++)
    {
        *(__IO uint32_t*) (SRAM_BANK_ADDR + 4*counter) = (uint32_t)0x00;
    }

    /* 向整个SDRAM写入数据  32位 */
    for (counter = 0; counter < SRAM_SIZE/4; counter++)
    {
        *(__IO uint32_t*) (SRAM_BANK_ADDR + 4*counter) = (uint32_t)(uwWritedata_32b + counter);
    }

    /* 读取 SDRAM 数据并检测*/
    for (counter = 0; counter<SRAM_SIZE/4; counter++)
    {
        uwReaddata_32b = *(__IO uint32_t*)(SRAM_BANK_ADDR + 4*counter);

        if (uwReaddata_32b != (uint32_t)(uwWritedata_32b + counter))
        {
            LOG_E("32bit data read/write error!");
            return -RT_ERROR;
        }
    }

    LOG_D("SRAM test ok!");
#endif

    return RT_EOK;
}
MSH_CMD_EXPORT(sram_test, sram test)
#endif /* FINSH_USING_MSH */
#endif /* DRV_DEBUG */

#endif /* BSP_USING_SRAM */


